In the fields of wired and wireless communication, the necessity for high-speed mass data transmission is increasing. To this end, use of a high-speed serial interface transmitting a clock and data through the same signal line has been increasing lately. When the high-speed interface operates, a circuit having a low jitter characteristic is required to maintain performance. The high-speed serial interface generally has a clock and data recovery (CDR) circuit employing a phase-locked loop (PLL) for clock recovery and data sampling therein. A part of the CDR circuit having the highest probability of causing jitter is a voltage controlled oscillator (VCO). The overall jitter characteristic of the VCO is determined by several jitter sources such as thermal noise, flicker noise, and supply noise. Thus, a VCO needs to be designed to be insensitive to the several jitter sources and have a low jitter characteristic.